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[ARM ์ปดํ“จํ„ฐ ๊ตฌ์กฐ] delay_loop ๊ตฌํ˜„ ๋ฐ ๊ฐ€์ƒ ๋จธ์‹  ํ…Œ์ŠคํŠธ ๊ตฌํ˜„ ๊ณผ์ œ - ํ•ด๊ฒฐ ๊ณผ์ • - ๋„์ „1ํŠธ

by EunBird 2023. 6. 12.

Problem1

; Delay ๋ฃจํ”„ ์ฝ”๋“œ  
lowlevel_init
    ; Add delay of 40ms
		LDR r3, =600000 ; ๋”œ๋ ˆ์ด ๋ฃจํ”„๋ฅผ 600,000๋ฒˆ ์ˆ˜ํ–‰ํ•˜๋„๋ก ์ง€์ •
	 
delay_loop
    SUBS r3, r3, #1
    BNE delay_loop

ํ”ผ๋“œ๋ฐฑ ์ฃผ์‹  ๋ถ€๋ถ„ ์ฐธ๊ณ ํ•˜์—ฌ 60Mhz ์—์„œ 40ms ์˜ ๋”œ๋ ˆ์ด๋ฅผ ๋งŒ๋“œ๋Š” ์ •์ƒ์ ์ธ ๋ฐฉ๋ฒ•์œผ๋กœ ๋”œ๋ ˆ์ด ๋ฃจํ”„ ๋ฐ˜๋ณต ํšŸ์ˆ˜๋ฅผ ์ฐพ์•„๋ƒˆ์Šต๋‹ˆ๋‹ค.

 

๐Ÿ’ก 60 MHz --> 1์ดˆ์— 60,000,000 ๋ฒˆ์˜ ํด๋Ÿญ ์‹ ํ˜ธ

40ms = 0.04s ⇒ ํด๋Ÿญ ์ฃผํŒŒ์ˆ˜ x ์‹œ๊ฐ„ = 60,000,000 Hz x 0.04 ์ดˆ = 2,400,000 ํด๋Ÿญ ์ฃผํŒŒ์ˆ˜

๋”ฐ๋ผ์„œ, 0.04 ์ดˆ (40 ms)์—๋Š” 2,400,000 ๋ฒˆ์˜ ํด๋Ÿญ ์ฃผํŒŒ์ˆ˜๊ฐ€ ๋ฐœ์ƒํ•ฉ๋‹ˆ๋‹ค.

 

๐Ÿ’ก ์ด๋•Œ, ๋”œ๋ ˆ์ด ๋ฃจํ”„(SUBS, BNE ๋ช…๋ น)์—์„œ 4์‚ฌ์ดํด์ด ์†Œ๋ชจ๋˜๊ธฐ ๋•Œ๋ฌธ์—
(์‹ค์ œ ๋””๋ฒ„๊น…ํ•ด๋ณด๋ฉด ๋ฃจํ”„ ํ•œ๋ฒˆ๋‹น 4states ์ฆ๊ฐ€ํ•จ์„ ํ™•์ธ)

0.04ms (2,400,000์‚ฌ์ดํด)์„ ์†Œ๋ชจํ•˜๊ธฐ ์œ„ํ•ด์„œ๋Š”

๋”œ๋ ˆ์ด ๋ฃจํ”„๋ฅผ 2400000 / 4 = 600000 ๋ฒˆ ์ง€๋‚˜๋ฉด ๋จ ๋”ฐ๋ผ์„œ r1์˜ ์ดˆ๊ธฐ๊ฐ’์€ 600,000์œผ๋กœ ์„ค์ •

 

delay ๋ฃจํ”„ ์ˆ˜ํ–‰ ํ›„ states ๊ฐ’์ด 24000004 ๊ฐ€ ๋˜๋Š” ๊ฒƒ์„ ํ™•์ธ


Problem2

ROM๊ณผ RAM์˜ ์ฃผ์†Œ๋ฅผ ์„ค์ •ํ•˜๊ณ  ๋ฃจํ”„ ๋ฐ˜๋ณต ํšŸ์ˆ˜๋ฅผ 0x1000์œผ๋กœ ์ง€์ •.

์ดํ›„์— copy_code_block ์—์„œ ROM์œ„์น˜์—์„œ RAM์œ„์น˜๋กœ 4๋ฐ”์ดํŠธ์”ฉ ๋ณต์‚ฌ.

ํ•œ๋ฒˆ ๋ณต์‚ฌํ•  ๋•Œ๋งˆ๋‹ค 0x4์”ฉ ๊ฐ์†Œ์‹œ์ผœ์„œ r2๊ฐ’์ด 0์ด ๋ ๋•Œ๊นŒ์ง€๋งŒ ๋ณต์‚ฌ.

์ดํ›„ 0x40000000 ์œ„์น˜๋กœ ์ ํ”„

; Setting ROM and RAM address
    LDR r0, =0x40000000 ; RAM ์˜์—ญ ์‹œ์ž‘ ์ฃผ์†Œ
    LDR r1, =0x0 ; ROM ์˜์—ญ ์‹œ์ž‘ ์ฃผ์†Œ
    LDR r2, =0x1000 ; ๋ณต์‚ฌํ•  ์ฝ”๋“œ ๋ธ”๋ก ํฌ๊ธฐ

copy_code_block   ; ROM -> RAM ์œผ๋กœ ์ฝ”๋“œ ๋ธ”๋ก ๋ณต์‚ฌ
    LDR r4, [r1], #4 ; ROM์œ„์น˜์—์„œ 4๋ฐ”์ดํŠธ ๋กœ๋“œํ•˜๊ณ  4๋ฐ”์ดํŠธ ์ฆ๊ฐ€
    STR r4, [r0], #4 ; ๋กœ๋“œํ•œ ๊ฐ’ RAM์œ„์น˜์— ์ €์žฅํ•˜๊ณ  ์ฃผ์†Œ 4๋ฐ”์ดํŠธ ์ฆ๊ฐ€
		SUBS r2, r2, #4 ; ๋‚จ์€ ๋ณต์‚ฌ ํšŸ์ˆ˜ ๊ณ„์‚ฐ  
		CMP r2, #0 
    BNE copy_code_block

; ----- ----- ------
    ; ๋ณต์‚ฌ ์ดํ›„ 
    LDR r0, =0x4000000
    BX r0  ; ๋ณต์‚ฌํ•œ ๊ฐ’๋“ค์ด ์žˆ๋Š” AM ์ฃผ์†Œ(0x40000000)๋กœ ์ด๋™

 


 

์ตœ์ข… ์ฝ”๋“œ.

arm 7TDMI ์–ด์…ˆ๋ธ”๋ฆฌ ์ฝ”๋“œ์ด๋‹ค.

 

	GLOBAL Reset_Handler
	AREA Reset, CODE, READONLY
	ENTRY

Reset_Handler
    
 
; Delay ๋ฃจํ”„ ์ฝ”๋“œ  
lowlevel_init
    ; Add delay of 40ms
		LDR r3, =600000 ; ๋”œ๋ ˆ์ด ๋ฃจํ”„๋ฅผ 600,000๋ฒˆ ์ˆ˜ํ–‰ํ•˜๋„๋ก ์ง€์ •
	 
delay_loop
    SUBS r3, r3, #1
    BNE delay_loop

; ----- ----- ------

; Setting ROM and RAM address
    LDR r0, =0x40000000 ; RAM ์˜์—ญ ์‹œ์ž‘ ์ฃผ์†Œ
    LDR r1, =0x0 ; ROM ์˜์—ญ ์‹œ์ž‘ ์ฃผ์†Œ
    LDR r2, =0x1000 ; ๋ณต์‚ฌํ•  ์ฝ”๋“œ ๋ธ”๋ก ํฌ๊ธฐ

copy_code_block   ; ROM -> RAM ์œผ๋กœ ์ฝ”๋“œ ๋ธ”๋ก ๋ณต์‚ฌ
    LDR r4, [r1], #4 ; ROM์œ„์น˜์—์„œ 4๋ฐ”์ดํŠธ ๋กœ๋“œํ•˜๊ณ  4๋ฐ”์ดํŠธ ์ฆ๊ฐ€
    STR r4, [r0], #4 ; ๋กœ๋“œํ•œ ๊ฐ’ RAM์œ„์น˜์— ์ €์žฅํ•˜๊ณ  ์ฃผ์†Œ 4๋ฐ”์ดํŠธ ์ฆ๊ฐ€
		SUBS r2, r2, #1 ; ๋‚จ์€ ๋ณต์‚ฌ ํšŸ์ˆ˜ ๊ณ„์‚ฐ  
		CMP r2, #0 ; 0 ์ธ์ง€ ํ™•์ธ
    BNE copy_code_block ; 0 ์•„๋‹ˆ๋ฉด ๋ฐ˜๋ณต

; ----- ----- ------
    ; ๋ณต์‚ฌ ์ดํ›„ 
    LDR r0, =0x40000000 ; ๋ณต์‚ฌํ•œ ์ฝ”๋“œ ๋ธ”๋ก ์ฃผ์†Œ
    BX r0  ; ๋ณต์‚ฌํ•œ ๊ฐ’๋“ค์ด ์žˆ๋Š” ์—๋ฎฌ๋ ˆ์ด์…˜ RAM ์ฃผ์†Œ(0x40000000)๋กœ ์ด๋™
		
END

0x4000000 ์œ„์น˜๋ถ€ํ„ฐ ๋ณต์‚ฌ ๋ฃจํ”„๋‹น 4๋ฐ”์ดํŠธ์”ฉ ๋ณต์‚ฌ๋˜์–ด ์“ฐ์—ฌ์ง€๋Š” ๊ฒƒ์„ ํ™•์ธ.

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